AD7013ARS datasheet(7/20 Pages) AD

7 / 20 page

REV. A

AD7013

–7–

RECEIVE SECTION TIMING

AA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND = 0 V,fMCLK = 6.2208 MHz;

A = TMIN to TMAX, unless otherwise noted)

MCLK (I)

RxCLK (O)

RxFRAME (O)

RxDATA (O)

I MSB

I LSB

15-BIT

I WORD

I/Q

FLAG BIT

15-BIT

Q WORD

Q LSB

Q MSB

I/Q

FLAG BIT

Q LSB

DxCLK (O)

I MSB

FINAL IQ PAIR PRIOR

TO POWER DOWN

CR14

NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT

I LSB

Q MSB

The last DxCLK edge which is

used to write to Command Reg

One, setting CR14 to One

The last DxCLK edge which is

used to write to Command Reg

One, setting CR14 to Zero

Figure 3. Receive Serial Interface Timing with 4

× Sampling of the Symbol Rate (CR10 = 1)

Limit at

Parameter

A = –40°C to +85°C

Units

Description

Power-Up Receive to RxCLK

10240t

ns max

CR13 = 0, Rx Offset Autocalibration On

6144t

ns max

CR13 = 1, Rx Offset Autocalibration Off

ns min

Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge

ns max

RxCLK Cycle Time; CR10 = 1; 4

× Sampling of the Symbol Rate

1–20

ns min

RxCLK High Pulse Width; CR10 = 1

1–20

ns min

RxCLK Low Pulse Width; CR10 = 1

–10

ns min

RxCLK Rising Edge to RxFRAME Rising Edge

ns max

32t

RxFRAME Cycle Time; CR10 = 1

RxFRAME High Pulse Width; CR10 = 1

–10

ns min

RxDATA Valid After RxCLK Rising Edge

ns max

10t

ns min

DxCLK Rising Edge to Last Falling Edge RxCLK

64t

ns max

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