AD7450 datasheet(22/24 Pages) AD

22 / 24 page

REV. PrJ

PRELIMINARY TECHNICAL DATA

–22–

AD7450

AD7450*

SDATA

*ADDITIONAL PINS OMITTED FOR CLARITY

MISO/PMC0

SCLK/PMC2

SCLK

SS/PMC3

MC68HC16*

Figure 27. Interfacing to the MC68HC16

AD7450 to DSP56xxx

The connection diagram in figure 28 shows how the

AD7450 can be connected to the SSI (Synchronous Serial

Interface) of the DSP56xxx family of DSPs from

Motorola. The SSI is operated in Synchronous Mode

(SYN bit in CRB =1) with internally generated 1-bit clock

period frame sync for both Tx and Rx (bits FSL1 =1 and

FSL0 =0 in CRB). Set the word length to 16 by setting

bits WL1 =1 and WL0 = 0 in CRA. To implement the

power-down mode on the AD7450 then the word length

can be changed to 8 bits by setting bits WL1 = 0 and WL0

= 0 in CRA. It should be noted that for signal processing

applications, it is imperative that the frame

synchronisation signal from the DSP56xxx will

provideequidistant sampling.

AD7450*

SDATA

*ADDITIONAL PINS OMITTED FOR CLARITY

SRD

SCLK

SR2

DSP56xxx*

Figure 28. Interfacing to the DSP56xx

AD7450 데이터시트(PDF) 22 Page - Analog Devices