PCAL9535APW datasheet(7/46 Pages) NXP

7 / 46 page

PCAL9535A

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Product data sheet

Rev. 1 — 28 September 2012

7 of 46

NXP Semiconductors

PCAL9535A

Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O

6.2.2 Input port register pair (00h, 01h)

The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins,

regardless of whether the pin is defined as an input or an output by the Configuration

The default value ‘X’ is determined by the externally applied logic level. An Input port

registers”.

6.2.3 Output port register pair (02h, 03h)

The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins

defined as outputs by the Configuration register. Bit values in these registers have no

effect on pins defined as inputs. In turn, reads from these registers reflect the value that

was written to these registers, not the actual pin value. A register pair write is described in

Section 7.1 and a register pair read is described in Section 7.2.

Table 5.

Input port 0 register (address 00h)

Bit

Symbol

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

Default

Table 6.

Input port 1 register (address 01h)

Bit

Symbol

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

I1.1

I1.0

Default

Table 7.

Output port 0 register (address 02h)

Bit

Symbol

O0.7

O0.6

O0.5

O0.4

O0.3

O0.2

O0.1

O0.0

Default

Table 8.

Output port 1 register (address 03h)

Bit

Symbol

O1.7

O1.6

O1.5

O1.4

O1.3

O1.2

O1.1

O1.0

Default

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