REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–17–

parallel interface. The serial interface is multiplexed on

the parallel data bus. The AD7667 digital interface also

accommodates both 3 V or 5 V logic by simply connecting

the OVDD supply pin of the AD7667 to the host system

interface digital supply. Finally, by using the OB/

2C in-

put pin, both two’s complement or straight binary coding

can be used.

The two signals

CS and RD control the interface. CS and RD

have a similar effect because they are OR’d together inter-

nally. When at least one of these signals is high, the interface

outputs are in high impedance. Usually,

CS allows the selec-

tion of each AD7667 in multicircuits applications and is held

low in a single AD7667 design.

RD is generally used to

enable the conversion result on the data bus.

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

1

2

3

14

15

16

D15

D14

D2

D1

D0

X

EXT/INT = 0

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

Figure 16. Master Serial Data Timing for Reading (Read After Convert)

EXT/INT = 0

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

D15

D14

D2

D1

D0

X

12

3

14

15

16

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)