AD7836AS datasheet(3/12 Pages) AD

부품명	AD7836AS

상세설명	LC2MOS Quad 14-Bit DAC

PDF	12 Pages

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AD7836

–3–

REV. A

TIMING SPECIFICATIONS1

Parameter

Limit at TMIN, TMAX

Units

Description

ns min

A0, A1, A2 to WR Setup Time

ns min

A0, A1, A2 to WR Hold Time

ns min

CS to WR Setup Time

ns min

WR to CS Hold Time

ns min

WR Pulsewidth

ns min

Data Setup Time

4.5

ns min

Data Hold Time

ns min

WR Pulse Interval

µs typ

Settling Time

t10

300

ns max

CLR Pulse Activation Time

NOTES

1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2Rise and fall times should be no longer than 50 ns.

Specifications subject to change without notice.

(VCC = +5 V

5%; VDD = +15 V

5%; VSS = –15 V

5%; AGND = DGND = 0 V)

t10

DATA

VOUT

CLR

A0, A1, A2

VOUT

Figure 1. Timing Diagram

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