AD7839AS datasheet(3/12 Pages) AD

3 / 12 page

–3–

REV. 0

AD7839

(These characteristics are included for Design Guidance and are not subject

to production testing.)

AC PERFORMANCE CHARACTERISTICS

Parameter

Units

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

µs typ

Full-Scale Change to

±1/2 LSB. DAC Latch Contents Alternately

µs max

Loaded with All 0s and All 1s

Slew Rate

0.7

µs typ

Digital-to-Analog Glitch Impulse

230

nV-s typ

Measured with VREF(+) = +5 V, VREF(–) = –5 V. DAC Latch

Alternately Loaded with 0FFF Hex and 1000 Hex. Not Dependent

on Load Conditions

Channel-to-Channel Isolation

dB typ

See Terminology

DAC-to-DAC Crosstalk

nV-s typ

See Terminology

Digital Crosstalk

0.2

nV-s typ

Feedthrough to DAC Output Under Test Due to Change in Digital

Input Code to Another Converter

Digital Feedthrough

0.1

nV-s typ

Effect of Input Bus Activity on DAC Output Under Test

Output Noise Spectral Density

@ 1 kHz

200

nV/

√Hz typ

All 1s Loaded to DAC. VREF(+) = VREF(–) = 0 V

Specifications subject to change without notice.

TIMING SPECIFICATIONS1, 2

Parameter

Limit at TMIN, TMAX

Units

Description

ns min

Address to

WR Setup Time

ns min

Address to

WR Hold Time

ns min

CS Pulsewidth Low

ns min

WR Pulsewidth Low

ns min

CS to WR Setup Time

ns min

WR to CS Hold Time

ns min

Data Setup Time

ns min

Data Hold Time

µs typ

Settling Time

t10

300

ns max

CLR Pulse Activation Time

t11

ns min

LDAC Pulsewidth Low

NOTES

1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2Rise and fall times should be no longer than 50 ns.

Specifications subject to change without notice.

t10

LDAC

CLR

A0, A1, A2

DATA

VOUT

t11

Figure 1. Timing Diagram

(VCC = +5 V

5%; VDD = +15 V

5%; VSS = –15 V

5%; GND = DUTGND = 0 V)

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