MSC8152 datasheet(49/68 Pages) FREESCALE

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Electrical Characteristics

MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 5

Freescale Semiconductor

2.6.5.2

RGMII AC Timing Specifications

Table 34 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.

Table 35 presents the RGMII AC timing specification for applications required non-delayed clock on board.

Figure 25 shows the RGMII AC timing and multiplexing diagrams.

Table 34. RGMII at 1 Gbps2 with On-Board Delay3 AC Timing Specifications

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)4

tSKEWT

–-0.5

—

0.5

Data to clock input skew (at receiver) 4

tSKEWR

1—

2.6

Notes:

At recommended operating conditions with VDDIO of 2.5 V ± 5%.

RGMII at 100 Mbps support is guaranteed by design.

Program GCR4 as 0x00000000.

This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and

less than 2.0 ns is added to the associated clock signal.

Table 35. RGMII at 1 Gbps2 with No On-Board Delay3 AC Timing Specifications

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)4

tSKEWT

–2.6

—

–1.0

Data to clock input skew (at receiver)4

tSKEWR

–0.5

—

0.5

Notes:

At recommended operating conditions with VDDIO of 2.5 V ± 5%.

RGMII at 100 Mbps support is guaranteed by design.

GCR4 should be programmed as 0x000CC330.

This implies that PC board design requires clocks to be routed with no additional trace delay

Figure 25. RGMII AC Timing and Multiplexing

GTX_CLK

tSKEWT

TX_CTL

txd[7:4]

txd[3:0]

(At Transmitter)

TXD[3:0]

RX_CTL

rxd[8:5]

rxd[3:0]

RXD[3:0]

RX_CLK

(At Receiver)

tSKEWR

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