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AD8522 데이터시트(PDF) 6 Page - Analog Devices |
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AD8522 데이터시트(HTML) 6 Page - Analog Devices |
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6 / 8 page ![]() AD8522 input register and transferring the 12 bits of data into the de- coded address determined by the address bits A and B in the se- rial input register. Unipolar Output Operation This is the basic mode of operation for the AD8522. The AD8522 has been designed to drive loads as low as 820 Ω in parallel with 500 pF. The code table for this operation is shown in Table III. Table III. Unipolar Code Table Hexadecimal Decimal Analog Number in Number in Output DAC Register DAC Register Voltage (V) FFF 4095 +4.095 801 2049 +2.049 800 2048 +2.048 7FF 2047 +2.047 000 0 0 5 2 0 1 3 4 10 100 100k 10k 1k RL TIED TO AGND DATA = FFFH VDD = +5V TA = +25 °C RL TIED TO +5V DATA = 000H LOAD RESISTANCE – Ω VINH = +5V VINL = 0V Figure 6. Output Swing vs. Load 80 60 40 20 0 –20 –40 –60 –80 123 OUTPUT VOLTAGE – Volts DATA = 800H POSITIVE CURRENT LIMIT NEGATIVE CURRENT LIMIT Figure 9. IOUT vs. VOUT 5.2 5.0 4.8 4.6 4.4 4.2 4.0 0.01 0.1 100 10 1.0 OUTPUT LOAD CURRENT – mA ∆VFS ≤ 1 LSB DATA = FFFH TA = +25°C PROPER OPERATION WHEN VDD SUPPLY VOLTAGE IS ABOVE CURVE Figure 7. Minimum Supply Voltage vs. Load Current 100 90 10 0% 100µs/DIV TA = +25°C NBW = 1MHz Figure 10. Broadband Noise 1 10 1000 100 100 1 0.1 10 0.01 +85 °C –55 °C +25 °C VDD = +5V DATA = 000H VIH = 5.0V VIL = 0.0V OUTPUT SINK CURRENT – µA Figure 8. Pull-Down Voltage vs. Out- put Sink Current Capability 9 8 7 6 5 4 3 2 1 0 01 3 4 5 2 VDD = +4.5V VDD = +5V TA = +25°C LOGIC INPUT VOLTAGE VINH – Volts Figure 11. Supply Current vs. Logic Input Voltage Typical Performance Characteristics is possible down to +4.3 V. The minimum operating supply voltage versus load current plot, in Figure 7, provides informa- tion for operation below VDD = +4.5 V. TIMING AND CONTROL The AD8522 has a 16-bit serial input register that accepts clocked in data when the CS pin is active low. The DAC regis- ters are updated by the Load Enable (LDA and LDB) pins. The AD8522 offers two modes of data loading. The first mode, hardware-load, directs the data currently clocked into the serial shift register into either the DAC A or the DAC B register or both depending on the external active low strobing of the LDA or LDB pin. Serial data register bit Sf/Hd must be low for this mode to be in effect. The second mode of operation is software-load which is de- signed to minimize the number of control lines connected to the AD8522. In this mode of operation the LDA and LDB pins act as one control input taking the present contents of the serial –6– REV. A |
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