AD876ARS datasheet(3/16 Pages) AD

3 / 16 page

AD876

REV. B

–3–

DIGITAL SPECIFICATIONS

AD876

Parameter

Symbol

DRVDD

Min

Typ

Max

Units

LOGIC INPUT

High Level Input Voltage

VIH

3.0

2.4

5.0

4.0

5.25

4.2

Low Level Input Voltage

VIL

3.0

0.6

5.0

1.0

5.25

1.05

High Level Input Current

IIH

5.0

–10

+10

µA

Low Level Input Current

IIL

5.0

–50

+50

µA

Low Level Input Current (CLK Only)

IIL

5.0

–10

+10

µA

Input Capacitance

CIN

5pF

LOGIC OUTPUTS

High Level Output Voltage

VOH

(IOH = 50

µA)

3.0

2.4

5.0

3.8

(IOH = 0.5 mA)

5.0

2.4

Low Level Output Voltage

VOL

(IOL = 50

µA)

3.6

0.7

5.25

1.05

(IOL = 0.6 mA)

5.25

0.4

Output Capacitance

COUT

5pF

Output Leakage Current

IOZ

–10

µA

Specifications subject to change without notice.

TIMING SPECIFICATIONS

Symbol

Min

Typ

Max

Units

Maximum Conversion Rate1

MHz

Clock Period

Clock High

tCH

Clock Low

tCL

Output Delay

tOD

Pipeline Delay (Latency)

3.5

Clock Cycles

Aperture Delay Time

Aperture Jitter

NOTE

1Conversion rate is operational down to 10 kHz without degradation in specified performance.

OUT

DATA N-4

DATA N-3

DATA N-2

DATA N-1

DATA N

SAMPLE N

SAMPLE N+1

SAMPLE N+2

AIN

CLK

tCL

tCH

tOD

Figure 1. Timing Diagram

(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +3.3 V, VREFT = +4.0 V, VREFB = +2.0 V,

fCLOCK = 20 MSPS, CL = 20 pF unless otherwise noted)

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