AD9772EB datasheet(19/32 Pages) AD

19 / 32 page

REV. A

AD9772A

–19–

AD9772A

CLK+

CLKVDD

CLK–

CLKCOM

0.1 F

ECL/PECL

Figure 21. Differential Clock Interface

The quality of the clock and data input signals are important in

achieving the optimum performance. The external clock driver

circuitry should provide the AD9772A with a low jitter clock

input which meets the min/max logic levels while providing fast

edges. Although fast clock edges help minimize any jitter that

will manifest itself as phase noise on a reconstructed waveform,

the high gain-bandwidth product of the AD9772A’s differential

comparator can tolerate sine wave inputs as low as 0.5 V p-p,

with minimal degradation in its output noise floor.

Digital signal paths should be kept short and run lengths

matched to avoid propagation delay mismatch. The insertion of

a low- value resistor network (i.e., 50

Ω to 200 Ω) between the

AD9772A digital inputs and driver outputs may be helpful in

reducing any overshooting and ringing at the digital inputs that

contribute to data feedthrough.

SLEEP MODE OPERATION

The AD9772A has a SLEEP function that turns off the output

current and reduces the analog supply current to less than 6 mA

over the specified supply range of 2.8 V to 3.2 V. This mode

can be activated by applying a Logic Level 1 to the SLEEP

pin. The AD9772A takes less than 50 ns to power down and

approximately 15

µs to power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9772A is dependent on

several factors, including:

1. AVDD, PLLVDD, CLKVDD, and DVDD, the power sup-

ply voltages.

2. IOUTFS, the full-scale current output.

3. fDATA, the update rate.

4. the reconstructed digital input waveform.

The power dissipation is directly proportional to the analog

supply current, IAVDD, and the digital supply current, IDVDD.

IAVDD is directly proportional to IOUTFS, and is insensitive

to fDATA.

Conversely, IDVDD is dependent on both the digital input

waveform and fDATA. Figure 22 shows IDVDD as a function of

full-scale sine wave output ratios (fOUT/fDATA) for various update

rates with DVDD = 3 V. The supply current from CLKVDD

and PLLVDD is relatively insensitive to the digital input wave-

form, but shown directly proportional to the update rate as

shown in Figure 23.

RATIO –

fOUT/fDATA

100

0.0

0.1

0.2

0.3

0.4

0.5

fDATA = 160MSPS

fDATA = 125MSPS

fDATA = 100MSPS

fDATA = 65MSPS

fDATA = 50MSPS

fDATA = 25MSPS

Figure 22. IDVDD vs. Ratio @ DVDD = 3.3 V

fDATA – MSPS

100

150

200

IPLLVDD

ICLKVDD

Figure 23. IPLLVDD and ICLKVDD vs. fDATA

APPLYING THE AD9772A OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configura-

tions for the AD9772A. Unless otherwise noted, it is assumed

that IOUTFS is set to a nominal 20 mA for optimum performance.

For applications requiring the optimum dynamic performance,

a differential output configuration is highly recommended. A

differential output configuration may consist of either an RF

transformer or a differential op amp configuration. The trans-

former configuration provides the optimum high-frequency

performance and is recommended for any application allowing

for ac coupling. The differential op amp configuration is suitable

for applications requiring dc coupling, a bipolar output, signal

gain, and/or level-shifting.

A single-ended output is suitable for applications requiring a

unipolar voltage output. A positive unipolar output voltage will

result if IOUTA and/or IOUTB is connected to an appropriately-sized

load resistor, RLOAD, referred to ACOM. This configuration may

be more suitable for a single-supply system requiring a dc-coupled,

ground-referred output voltage. Alternatively, an amplifier could

be configured as an I-V converter, thus converting IOUTA or

IOUTB into a negative unipolar voltage. This configuration pro-

vides the best dc linearity since IOUTA or IOUTB is maintained at

a virtual ground.

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