| 전자부품 데이터시트 검색엔진 |
|
AD9775EB 데이터시트(PDF) 39 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9775EB 데이터시트(HTML) 39 Page - Analog Devices |
|
39 / 48 page ![]() REV. 0 AD9775 –39– SIGNAL GENERATOR CLK+/CLK– DATACLK LECROY PULSE GENERATOR TRIG INP AWG2021 OR DG2020 INPUT CLOCK DAC1, DB11–DB0 AD9775 DAC2, DB11–DB0 40-PIN RIBBON CABLE JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON SOLDERED/IN UNSOLDERED/OUT JP1 – JP2 – JP3 – JP5 – JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – Figure 55. Test Configuration for AD9775 in Two Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate, DAC Output Data Rate = Signal Generator Frequency Interpolation Rate SIGNAL GENERATOR CLK+/CLK– ONEPORTCLK LECROY PULSE GENERATOR TRIG INP AWG2021 OR DG2020 INPUT CLOCK DAC1, DB11–DB0 AD9775 DAC2, DB11–DB0 JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON SOLDERED/IN UNSOLDERED/OUT JP1 – JP2 – JP3 – JP5 – JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – Figure 56. Test Configuration for AD9775 in One Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency Interpolation Rate |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |