AD9852ASQ datasheet(6/42 Pages) AD

6 / 42 page

AD9852

–6–

REV. 0

No.

Pin Name

Function

DACBP

Common Bypass Capacitor Connection for Both DACs. A 0.01

µF chip cap from this pin to AVDD

improves harmonic distortion and SFDR slightly. No connect is permissible (slight SFDR degradation).

DAC RSET

Common Connection for Both DACs to Set the Full-Scale Output Current. RSET = 39.9/IOUT.

Normal RSET range is from 8 k

Ω (5 mA) to 2 kΩ (20 mA).

PLL FILTER

This pin provides the connection for the external zero compensation network of the REFCLK

Multiplier’s PLL loop ﬁlter. The zero compensation network consists of a 1.3 k

Ω resistor in series

with a 0.01

µF capacitor. The other side of the network should be connected to AVDD as close as

possible to Pin 60. For optimum phase noise performance, the REFCLK Multiplier can be bypassed

by setting the “Bypass PLL” bit in control register 1E.

DIFF CLK

Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK

and REFCLKB ENABLE (Pins 69 and 68 respectively). The minimum differential signal amplitude

required is 800 mV p-p. The centerpoint or common-mode range of the differential signal ranges

from 1.6 V to 1.9 V.

REFCLKB

The Complementary (180 Degrees Out-of-Phase) Differential Clock Signal. User should tie this pin

high or low when single-ended clock mode is selected. Same signal levels as REFCLK.

REFCLK

Single-Ended Reference Clock Input or One of Two Differential Clock Signals. Normal 3.3 V CMOS

logic levels or 1 V p-p sine wave centered about 1.6 V.

S/P SELECT

Selects Between Serial Programming Mode (Logic LOW) and Parallel Programming Mode

(Logic High).

MASTER

Initializes the serial/parallel programming bus to prepare for user programming; sets programming

RESET

registers to a “do-nothing” state deﬁned by the default values seen in the Table V. Active on logic

high. Asserting MASTER RESET is essential for proper operation upon power-up.

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