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AD9857/PCB 데이터시트(PDF) 25 Page - Analog Devices |
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AD9857/PCB 데이터시트(HTML) 25 Page - Analog Devices |
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25 / 31 page ![]() AD9857 –25– REV. 0 I0 TxENABLE PDCLK D<13:0> Q1 I1 Q0 Q2 I2 I0 Q0 I1 Q1 SYSCLK/N SYSCLK/2N SYSCLK/4N SIGNAL PATH I SIGNAL PATH Q INVCIC CLOCK LATENCY THROUGH DATA ASSEMBLER LOGIC IS 3 PDCLK CYCLES INVERSE CIC FILTER SETUP TIME DON'T CARE Figure 31. Latency from D<13:0> to Signal Processing Chain, Four PDCLK Cycles I0 TxENABLE PDCLK D<13:0> Q1 I1 Q0 Q2 I2 I0 Q0 I1 Q1 SYSCLK/N SYSCLK/2N SYSCLK/4N SIGNAL PATH I SIGNAL PATH Q INVCIC CLOCK LATENCY THROUGH DATA ASSEMBLER LOGIC IS 3 PDCLK CYCLES INVERSE CIC FILTER SETUP TIME DON'T CARE Q3 I3 Figure 32. Latency from D<13:0> to Signal Processing Chain, Five PDCLK Cycles |
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