EVAL-ADE7752EB datasheet(3/10 Pages) AD

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REV. PrB 08/01

PRELIMINARY TECHNICAL DATA

3–

ADE7752

TIMING CHARACTERISTICS1, 2

Parameter

Units

Test Conditions/Comments

275

F1 and F2 Pulsewidth (Logic High)

See Table III

sec

Output Pulse Period. See Transfer Function Section

1/2 t2

sec

Time Between F1 Falling Edge and F2 Falling Edge

3, 4

CF Pulsewidth (Logic High)

See Table IV

sec

CF Pulse Period. See Transfer Function Section

CLKIN/4

sec

Minimum Time Between F1 and F2 Pulse

NOTES

1Sample tested during initial release and after any redesign or process change that may affect this parameter.

2See Figure 1.

3The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.

4The CF pulse is always 1 µs in the high frequency mode. See Frequency Outputs section and Table IV.

Specifications subject to change without notice.

ORDERING GUIDE

Model

Package Description

Package Option

ADE7752AR

SOIC Package

R-24

EVAL-ADE7752EB ADE7752 Evaluation

Board

(VDD = 5 V

5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz,

TMIN to TMAX = –40 C to +85 C)

Figure 1. Timing Diagram for Frequency Outputs

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