ADM1021

–12–

REV. 0

APPLICATION CIRCUITS

Figure 18 shows a typical application circuit for the ADM1021,

using a discrete sensor transistor connected via a shielded,

twisted pair cable. The pull-ups on SCLK, SDATA and

ALERT

are required only if they are not already provided elsewhere in

the system.

The SCLK, and SDATA pins of the ADM1021 can be inter-

faced directly to the SMBus of an I/O controller such as the

Intel PCI ISA IDE Xcelerator (PIIX4) chip type 82371AB.

Figure 19 shows how the ADM1021 might be integrated into a

system using this type of I/O controller.

USB PORT 1

MAIN MEMORY

(DRAM)

BUILT-IN

SENSOR

PROCESSOR

HOST BUS

SECOND LEVEL

CACHE

HOST-TO-PCI

BRIDGE

MAIN MEMORY

(DRAM)

PCI BUS (3.3V OR 5V 30/33MHz)

PCI SLOTS

D– D+

ADM1021

USB PORT 2

ALERT SCLK SDATA

CD ROM

HARD

DISK

BMI IDE

ULTRA DMA/33

8237 1AB

(PIIX4)

HARD

DISK

GPI[I,O] (30+)

AUDIO

SERIAL PORT

PARALLEL PORT

FLOPPY DISK

CONTROLLER

INFRARED

SMBUS

KEYBOARD

BIOS

ISA/EIO BUS

(3.3V, 5V TOLERANT)

Figure 19. Typical System Using ADM1021

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Shrink Small Outline Package

(RQ-16)

16

9

8

1

0.197 (5.00)

0.189 (4.80)

0.244 (6.20)

0.228 (5.79)

PIN 1

0.157 (3.99)

0.150 (3.81)

SEATING

PLANE

0.010 (0.25)

0.004 (0.10)

0.012 (0.30)

0.008 (0.20)

0.025

(0.64)

BSC

0.059 (1.50)

MAX

0.069 (1.75)

0.053 (1.35)

0.010 (0.20)

0.007 (0.18)

0.050 (1.27)

0.016 (0.41)

8

0

STBY

SCLK

SDATA

ALERT

ADD0

ADD1

GND

D+

D–

0.1 F

ALL 10k

3.3V

TO PIIX4

CHIP

SET TO REQUIRED

ADDRESS

IN

OUT

I/O

C1*

SHIELD

2N3904

*C1 IS OPTIONAL

ADM1021

Figure 18. Typical ADM1021 Application Circuit