ADM1032ARM datasheet(2/12 Pages) AD

2 / 12 page

REV. 0

–2–

ADM1032–SPECIFICATIONS (T

A = TMIN to TMAX, VDD = VMIN to VMAX, unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER SUPPLY

Supply Voltage, VDD

3.0

3.30

5.5

Average Operating Supply Current, ICC

170

215

µA

0.0625 Conversions/Sec Rate

5.5

µA

Standby Mode

Undervoltage Lockout Threshold

2.35

2.55

2.8

VDD Input, Disables ADC, Rising Edge

Power-On Reset Threshold

2.4

TEMPERATURE-TO-DIGITAL CONVERTER

Local Sensor Accuracy

±1

±3

°C0 ≤ T

≤ 100°C, V

CC = 3 V to 3.6 V

Resolution

°C

Remote Diode Sensor Accuracy

±1

°C60°C ≤ TD ≤ 100°C, VCC = 3 V to 3.6 V

±3

°C0°C ≤ T

≤ 120°C

Resolution

0.125

°C

Remote Sensor Source Current

230

µA

High Level, Note 2

µA

Low Level, Note 2

Conversion Time

35.7

142.8

From Stop Bit to Conversion Complete

(Both Channels) One-Shot Mode with

Averaging Switched On

5.7

22.8

One-Shot Mode with Averaging Off

(i.e., Conversion Rate = 32 or 64

Conversions per Second)

OPEN-DRAIN DIGITAL OUTPUTS

(

THERM, ALERT)

Output Low Voltage, VOL

0.4

IOUT = –6.0 mA

High Level Output Leakage Current, IOH

0.1

µAV

OUT = VDD

SMBus INTERFACE

Logic Input High Voltage, VIH

2.1

VDD = 3 V to 5.5 V

SCLK, SDATA

Logic Input Low Voltage, VIL

0.8

VDD = 3 V to 5.5 V

Hysteresis

500

SCLK, SDATA

SMBus Output Low Sink Current

SDATA Forced to 0.6 V

ALERT Output Low Sink Current

ALERT Forced to 0.4 V

Logic Input Current, IIH, IIL

–1

µA

SMBus Input Capacitance, SCLK, SDATA

SMBus Clock Frequency

100

kHz

SMBus Timeout

Note 3

SMBus Clock Low Time, tLOW

4.7

µstLOW between 10% Points

SMBus Clock High Time, tHIGH

µst

HIGH between 90% Points

SMBus Start Condition Setup Time, tSU:STA

4.7

µs

SMBus Start Condition Hold Time, tHD:STA

µs

Time from 10% of SDATA to 90%

of SCLK

SMBus Stop Condition Setup Time, tSU:STO

µs

Time from 90% of SCLK to 10%

of SDATA

SMBus Data Valid to SCLK Rising Edge

250

Time for 10% or 90% of SDATA to

Time, tSU:DAT

10% of SCLK

SMBus Data Hold Time, tHD:DAT

300

µs

SMBus Bus Free Time, tBUF

4.7

µs

Between Start/Stop Condition

SCLK Falling Edge to SDATA

µs

Master Clocking in Data

Valid Time, tVD,DAT

SCLK, SDATA Rise Time, tR

µs

SCLK, SDATA Fall Time, tF

300

NOTES

1See Table VI for information on other conversion rates.

2Guaranteed by Design, not production tested.

3The SMBus timeout is a programmable feature. By default it is not enabled. Details on how to enable it are available in the SMBus section of this data sheet.

Specifications subject to change without notice.

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