ADP3422 datasheet(4/16 Pages) AD

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REV. 0

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ADP3422–SPECIFICATIONS

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

LOW-SIDE DRIVE CONTROL

Output Voltage (CMOS Output)

VDRVLSD

DPRSLP = H

0.4

DPRSLP = L

0.7 V

Output Current

IDRVLSD

DRVLSD = 1.5 V

DPRSLP = L

+0.4

DPRSLP = H

–0.4

OVER/REVERSE VOLTAGE

PROTECTION

Over-Voltage Threshold

VCOREFB,OVP

VCOREFB Rising

2.0

2.2

VCOREFB Falling

1.8

Reverse-Voltage Threshold

VCOREFB,RVP

VCOREFB Falling

–0.3

VCOREFB Rising

–0.05

Output Current (Open Drain Output) ICLAMP

VCLAMP = 1.5 V

VCOREFB = 2.2 V

µA

VCOREFB = VDACOUT = 1.25 V 1

NOTES

1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2Two test conditions:

1. PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V COREFB,BAD = 1.0 V at VVID = 1.25 V setting) to the COREFB pin right

after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay time.

2. PWRGD is forced to fail (VCOREFB,BAD = 1.0 V at VVID = 1.25 V setting) but gets into the CoreGood-window (VCOREFB,GOOD = 1.25 V) right after the moment that

BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified blanking delay time.

3Guaranteed by characterization.

4Measured from 50% of VID code transition amplitude to the point where V

DACOUT settles within

± 1% of its steady state value.

540 mV p-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.

6Measured between the 30% and 70% points of the output voltage swing.

Specifications subject to change without notice.

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