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ADSP2184 데이터시트(PDF) 17 Page - Analog Devices

부품명 ADSP2184
상세설명  DSP Microcomputer
PDF  31 Pages
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ADSP-2184
–17–
REV. 0
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements:
tBH
BR Hold after CLKOUT High1
0.25 tCK + 2
ns
tBS
BR Setup before CLKOUT Low1
0.25 tCK + 17
ns
Switching Characteristics:
tSD
CLKOUT High to
xMS, RD, WR Disable
0.25 tCK + 10
ns
tSDB
xMS, RD, WR Disable to BG Low
0
ns
tSE
BG High to xMS, RD, WR Enable
0
ns
tSEC
xMS, RD, WR Enable to CLKOUT High
0.25 tCK – 7
ns
tSDBH
xMS, RD, WR Disable to BGH Low2
0ns
tSEH
BGH High to xMS, RD, WR Enable2
0ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for
BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
CLKOUT
tSD
tSDB
tSE
tSEC
tSDBH
tSEH
tBS
BR
tBH
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
Figure 11. Bus Request–Bus Grant



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