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ADSP2181 데이터시트(PDF) 14 Page - Analog Devices |
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ADSP2181 데이터시트(HTML) 14 Page - Analog Devices |
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14 / 32 page ![]() REV. D ADSP-2181 –14– Parameter Min Max Unit Clock Signals and Reset Timing Requirements: tCKI CLKIN Period 50 150 ns tCKIL CLKIN Width Low 20 ns tCKIH CLKIN Width High 20 ns Switching Characteristics: tCKL CLKOUT Width Low 0.5tCK – 7 ns tCKH CLKOUT Width High 0.5tCK – 7 ns tCKOH CLKIN High to CLKOUT High 0 20 ns Control Signals Timing Requirement: tRSP RESET Width Low 5tCK 1 ns NOTE 1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). tCKOH tCKI tCKIH tCKIL tCKH tCKL tMH tMS CLKIN CLKOUT PF(2:0) * RESET *PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 8. Clock Signals |
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