ADV7175/ADV7176

REV. A

–23–

75

Ω

27

26

S VIDEO

31

32

5k

Ω

150

Ω

24

5k

Ω

MPU BUS

44

22

15

17

16

10, 19, 21

29, 36, 43

18

23

34

38–42,

2–9, 12–14

1, 11, 20, 28, 30, 37

0.1µF

0.01µF

0.1µF

0.1µF

10k

Ω

27MHz CLOCK

(SAME CLOCK AS USED BY

MPEG2 DECODER)

POWER SUPPLY DECOUPLING

FOR EACH POWER SUPPLY GROUP

10µF

33µF

GND

L1

(FERRITE BEAD)

25

33

GND

ALSB

HSYNC

FIELD/

VSYNC

BLANK

RESET

CLOCK

SDATA

SCLOCK

COMPOSITE

BLUE/

COMPOSITE/

U

RED/

CHROMA/

V

GREEN/

LUMA/

Y

COMP

P15–P0

75

Ω

75

Ω

75

Ω

35 SCRESET/RTC

ADV7175

ADV7176

“UNUSED

INPUTS

SHOULD BE

GROUNDED”

Figure 41. Recommended Analog Circuit Layout

The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is

guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if

13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the

ADV7175/ADV7176 in the correct sequence.

D

Q

CK

D

Q

CK

CLOCK

HSYNC

13.5MHz

Figure 42. Circuit to Generate 13.5 MHz