ADV7152LS85 datasheet(20/32 Pages) AD

20 / 32 page

ADV7152

–20–

REV. B

COMMAND REGISTER 2 (CR2)

(Address Reg (A7–A0) = 06H)

This register contains a number of control bits as shown in the

diagram. CR2 is a 10-bit wide register. However for program-

ming purposes, it may be considered as an 8-bit wide register

(CR28 and CR29 are both reserved).

The diagram shows the various operations under the control of

CR2. This register can be read from as well written to. In read

mode, CR28 and CR29 are both returned as zeros.

COMMAND REGISTER 2 BIT DESCRIPTION

R7 Trigger Polarity Control (CR20)

This bit determines whether the pixel data is latched into the

test registers on the rising or falling edge of R7, see “Test Diag-

nostics” section in Appendix 3.

IPLL Trigger Control (CR21)

This bit specifies whether the IPLL output is triggered from

BLANK

or SYNC.

SYNC

Recognition Control (CR22)

This bit specifies whether the video SYNC input is to be

encoded onto the IOG analog output or ignored.

Pedestal Enable Control (CR23)

This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedes-

tal is to be generated on the video outputs.

True-Color/Pseudo-Color Mode Control (CR27–CR24)

These 4 bits specify the various color modes. These include a

24-bit true-color mode, two 15-bit true-color modes and three

8-bit pseudo color modes.

RESERVED

TRUE-COLOR / PSEUDO-COLOR MODE CONTROL

8-BIT PSEUDO COLOR ON R7–R0

8-BIT PSEUDO COLOR ON G7–G0

8-BIT PSEUDO COLOR ON B7–B0

15-BIT TRUE COLOR ON

R7–R3, G7–G3,B7–B3

15-BIT TRUE COLOR ON

R7–R0, G6–G0

24-BIT TRUE COLOR

R7–R0, G7–G0, B7–B0

COLOR MODE

CR27 CR26

CR24

CR25

CR21

IPLL TRIGGER

CONTROL

SYNC

BLANK

R7 TRIGGER

POLARITY CONTROL

CR20

CR26

CR25

CR24

CR23

CR22

CR21

CR27

CR29

CR28

* THESE BITS ARE READ–ONLY

RESERVED BITS.

A READ CYCLE WILL

RETURN ZEROS "00."

IGNORE

DECODE

SYNC

RECOGNITION

CONTROL

CR22

PEDESTAL

ENABLE

CONTROL

0 IRE

7.5 IRE

CR23

Command Register 2 (CR2) (CR29–CR20)

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