CC3000MOD

www.ti.com

SWRS126 – NOVEMBER 2012

ESD PERFORMANCE

Because electrostatic discharge (ESD) can damage this integrated circuit, TI recommends handling all integrated

circuits (ICs) with appropriate precautions. Failure to observe proper handling and installation procedures can

cause damage. ESD damage can range from subtle performance degradation to complete device failure.

Precision ICs can be more susceptible to damage because very small parametric changes can cause devices

not to meet their published specifications.

Table 2 describes the ESD performance.

Table 2. ESD Performance

1000 V

500 V

(1)

JEDEC ESD HBM spec JS-001-2012

(2)

JEDEC ESD CDM spec 22C101E

space

MODULE SPECIFICATIONS

Absolute Maximum Ratings

Parameters

Pin

Min

Max

Unit

VBAT_IN

19

–0.5

+6.0

V

VIO_HOST

23

–0.5

+4.6

V

I2C and WL_RS232

27, 28, 29, 30, 6, 8

–0.5

+2.1

V

SPI interface

12, 13, 14, 15, 17

–0.5

+4.6

V

VBAT_SW_EN

26

–0.3

+6.0

V

Storage temperature range

–

–40

+85

°C

Recommended Operating Conditions

Rating

Condition

Sym

Min

Max

Unit

Operating ambient

–20

+70

°C

temperature

VBAT_IN

2.7

4.8

V

VIO_HOST supply voltage

1.8

3.6

V

SPI interface

High-level input voltage

VIO_HOST =

1.8 to 1.95 V

VIH

VIO_HOST x 0.65

V

1.95 to 2.7 V

1.6

2.7 to 3.6 V

2

Low-level input voltage

VIO_HOST =

1.8 to 1.95 V

VIL

VIO_HOST × 0.35

V

1.95 to 2.7 V

0.7

2.7 to 3.6 V

0.8

Input voltage

VI

0

3.6

V

Output voltage

Active state

VO

0

VIO_HOST

V

Input transition rise or fall

△t/△v

5

ns/V

rate

VBAT SW EN

High-level input voltage

VIH

1.1

5.5

V

Low-level input voltage

VIL

0

0.4

V

Copyright © 2012, Texas Instruments Incorporated

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