F28M36P63C2ZWTQ datasheet(4/202 Pages) TI

4 / 202 page

F28M36P63B2, F28M36P63C2

F28M36P53B2, F28M36P53C2, F28M36P33B2, F28M36P33C2

SPRS825 – OCTOBER 2012

www.ti.com

F28M36x (Concerto™) MCUs

......................... 1

3.1

Pin Assignments

.................................... 88

1.1

Features

............................................. 1

3.2

Terminal Functions

................................. 93

1.2

Description

........................................... 2

Device Operating Conditions

...................... 122

1.3

Functional Block Diagram

........................... 3

4.1

Absolute Maximum Ratings

....................... 122

Device Overview

........................................ 5

4.2

Recommended Operating Conditions

............. 122

2.1

Device Characteristics

............................... 6

4.3

Electrical Characteristics

.......................... 123

2.2

Memory Maps

........................................ 8

Electrical Specifications

............................ 124

2.3

Master Subsystem

.................................. 19

5.1

Current Consumption

............................. 124

2.4

Control Subsystem

................................. 25

5.2

Thermal Design Considerations

.................. 125

2.5

Analog Subsystem

.................................. 30

5.3

Timing Parameter Symbology

..................... 126

5.4

Clock Frequencies, Requirements, and

2.6

Master Subsystem NMIs

........................... 33

Characteristics

.................................... 127

2.7

Control Subsystem NMIs

........................... 33

5.5

Power Sequencing

................................ 130

2.8

Resets

.............................................. 35

Peripheral Information and Timings

............. 134

2.9

Internal Voltage Regulation and Monitoring

........ 40

6.1

Analog and Shared Peripherals

................... 134

2.10

Input Clocks and PLLs

............................. 44

6.2

Master Subsystem Peripherals

.................... 162

2.11

Master Subsystem Clocking

........................ 54

6.3

Control Subsystem Peripherals

................... 177

2.12

Control Subsystem Clocking

....................... 57

Device and Documentation Support

............. 196

2.13

Analog Subsystem Clocking

....................... 60

7.1

Device Support

.................................... 196

2.14

Shared Resources Clocking

........................ 60

7.2

Community Resources

............................ 197

2.15

Loss of Input Clock (NMI Watchdog Function)

..... 60

7.3

Trademarks

....................................... 198

2.16

GPIOs and Other Pins

.............................. 62

Mechanical Packaging and Orderable

2.17

Emulation/JTAG

.................................... 82

Information

............................................ 199

2.18

Code Security Module (CSM)

...................... 85

8.1

Thermal Data for Package

........................ 199

2.19

µCRC Module

...................................... 86

8.2

Packaging Information

............................ 199

Device Pins

............................................. 88

Contents

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