OP2177ARM datasheet(12/20 Pages) AD

12 / 20 page

REV. B

OP1177/OP2177/OP4177

–12–

Figure 6 is a scope photograph of the output of the OP1177 in

response to a 400 mV pulse. The load capacitance is 2 nF. The

circuit is configured in positive unity gain, the worst-case condition

for stability.

Placing an R-C network, as shown in Figure 8, parallel to the

load capacitance CL will allow the amplifier to drive higher

values of CL without causing oscillation or excessive overshoot.

There is no ringing and overshoot is reduced from 27% to 5%

using the snubber network.

Optimum values for RS and CS are tabulated in Table I for several

capacitive loads up to 200 nF. Values for other capacitive loads

can be determined experimentally.

Table I. Optimum Values for Capacitive Loads

CL (nF)

RS ( )CS

0.33

µF

6.8 nF

200

0.47

µF

0000

000

GND

VSY =

RL = 10k

CL = 2nF

TIME – 10 s/DIV

Figure 6. Capacitive Load Drive without Snubber

0000

000

GND

VSY =

RL = 10k

RS = 200

CL = 2nF

CS = 0.47 F

TIME – 10 s/DIV

Figure 7. Capacitive Load Drive with Snubber

V+

OP1177

400mV

VOUT

Figure 8. Snubber Network Configuration

CAUTION: The snubber technique cannot recover the loss of

bandwidth induced by large capacitive loads.

Stray Input Capacitance Compensation

The effective input capacitance in an op amp circuit, Ct, con-

sists of three components. These are: the internal differential

capacitance between the input terminals, the internal common

mode capacitance of each input to ground, and the external

capacitance including parasitic capacitance. In the circuit of

Figure 9, the closed-loop gain increases as the signal frequency

increases.

The transfer function of the circuit is:

()

sC R

indicating a zero at:

RR C

()

π 1// 2

Depending on the value of R1 and R2, the cutoff frequency of the

closed-loop gain may be well below the crossover frequency. In

this case, the phase margin,

Φm, can be severely degraded resulting

in excessive ringing or even oscillation.

A simple way to overcome this problem is to insert a capacitor in

the feedback path as shown in Figure 10.

The resulting pole can be positioned to adjust the phase margin.

Setting Cf = (R1/R2)Ct, achieves a phase margin of 90°.

VOUT

V+

OP1177

–

Figure 9. Stray Input Capacitance

VOUT

V+

OP1177

–

Figure 10. Compensation Using Feedback Capacitor

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