SSM2163

REV. 0

–3–

Timing Description

Timing

Symbol

Description

Min

Typ

Max

Units

Input Clock Pulse Width

50

ns

Input Clock Pulse Width

50

ns

Data Setup Time

25

ns

Data Hold Time

35

ns

Positive CLK Edge to End of Write

25

ns

Write to Clock Setup Time

35

ns

End of Load Pulse to Next Write

20

ns

End of Write to Start of Load

20

ns

Load Pulse Width

250

ns

Load Pulse Width (3-Wire Mode)

250

ns

Propagation Delay from Rising

10

80

160

ns

Clock to SDO Transition

Ω, C

NOTES

1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the positive

edge.

2. For SPI or microwire three-wire bus operation, tie LD to WRITE and use WRITE pulse to drive

both pins. (This generates an automatic internal LD signal.)

state.

4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain levels. Re-

fer to the Address/Data Decoding Truth Table.

5. Data must be sent MSB first.

D7

D6

D5

D4

D3

D2

D1

D0

1

0

1

DATA

0

1

0

1

0

1

0

CLK

DATA

CLK

1

SDO

1

0

WRITE & LOAD

WRITE & LOAD

Figure 1. Three-Wire Mode Timing Diagram