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CT1698 데이터시트(PDF) 5 Page - Aeroflex Circuit Technology |
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CT1698 데이터시트(HTML) 5 Page - Aeroflex Circuit Technology |
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5 / 7 page ![]() Aeroflex Circuit Technology SCDCT1698 REV A 6/12/98 Plainview NY (516) 694-6700 5 Drive Level Control Pins External Resistors may be connected from pins 5 and 6 to VEE or GND to change the Transmitter Output Level. If pins 5 and 6 are left open the CT1698 operates within the MIL-STD-1397 Type E specification. Resistors connected from pins 5 and 6 to VEE or Ground must be equal. Unequal resistors will result in a transmitter output offset level. The formula for peak to peak transmitter output swing with resistors connected between 5 and 6 to VEE is: The formula for peak to peak transmitter output swing with resistors connected between pins 5 and 6 to ground is: Functional Description and Pinout Pin # Pin Name Function Load or Drive 1 XFMR primary/ TX data output Transformer lead for connection to center conductor of tri-axial cable 2 XFMR secondary Secondary isolated winding, same phase as center conductor 3 TXDATA output/ RX data input Transmitter-receiver I/O pin (usually connected to pin 2) 4 No connection 5 Drive 2 Output level adjustment selected by resistor to GND or VEE 6 Drive 1 Output level ajustment selected by resistor to GND or VEE 7 -5 Volts 8 RX strobe Low level disables receiver 3 S loads 9 Power management input Controls transmitter power consumption in conjunction with pin 10 1 S load 10 Encoder enable Controls transmitter power consumption in conjunction with pin 9 1 S load 11 Case/signal GND 12 Case/signal GND 13 Decoded data envelope High after reception of first half bit; goes low after reception of last half bit (normally low in inactive state) 4 S drive 14 TP3 test point Alignment point: no electrical connection permitted 15 TP1 test point Alignment point: no electrical connection permitted 16 TP2 test point Alignment point: no electrical connection permitted 17 -5 Volts 18 TP4 test point Alignment point: no electrical connection permitted 19 ClockR Reconstructed clock; one clock pulse per input bit received 3 S drive 20 No connection 21 Decoded DataR NRZ reconstructed data. Sampled on clockR rising edge 3 S drive VOUT = 1.39 + 125 ± 15% Volts, REXT > 90Ω REXT pk-pk VOUT = 1.39 - 50 (VEE -2.5) ± 15% Volts, REXT > 180Ω pk-pk REXT |
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