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CT1815 데이터시트(PDF) 5 Page - Aeroflex Circuit Technology

부품명 CT1815
상세설명  CT1815 10MHz Low Level Serial Interface for MIL-STD-1397 Type D
PDF  7 Pages
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CT1815 데이터시트(HTML) 5 Page - Aeroflex Circuit Technology

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SCDCT1815 REV A 6/12/98 Plainview NY (516) 694-6700
5
Functional Description and Pinout
Pin
#
Pin Name
Function
Load or
Drive
1
No connection
2
No connection
3
XFMR secondary/
RX data input
Transmitter-receiver I/O pin
4
Test Point
No connection permitted
5
Test Point
No connection permitted
6
Test Point
No connection permitted
7
-5 Volts
8
RX strobe
Low level disables receiver
3 S loads
9
Power management
input
Controls transmitter power consumption in conjunction with pin 10
1 S load
10
Encoder enable
Controls transmitter power consumption in conjunction with pin 9
1 S load
11
Case/signal GND
12
Case/signal GND
13
Decoded data
envelope
High after reception of first half bit; goes low after reception of last
half bit (normally low in inactive state)
4 S drive
14
TP3 test point
Alignment point: no electrical connection permitted
15
TP1 test point
Alignment point: no electrical connection permitted
16
TP2 test point
Alignment point: no electrical connection permitted
17
-5 Volts
18
TP4 test point
Alignment point: no electrical connection permitted
19
ClockR
Reconstructed clock; one clock pulse per input bit received
3 S drive
20
No connection
21
Decoded DataR
NRZ reconstructed data. Sampled on clockR rising edge
3 S drive
22
No connection
23
+5 volts
24
+5 volts
25
10 MHz encoder shift
clock
One cycle required per data bit. Must be high in first half of bit cell
1 S load
26
NRZ serial input data
Serial input to be Manchester encoded with the 20 MHz gated CK
1 S load
27
Encode envelope
Must be high to enable transmission; must go low before reception
of last 20 MHz positive edge to complete transmission
1 S load
28
20 MHz gated clock
(encoder)
Each bit to be encoded requires two positive edges of the 20 MHz
CK. These edges must occur at 25ns and 75ns into the bit cell.
The end of transmission requires an additional edge in conjunction
with a logic low on the encode envelope. tR, tF < 5nsec.
1 S load
29
Master reset
reset pulse <15 nsec
Logic low resets encoder
2 S load
30
No connection
31
No connection
32
XFMR secondary/
RX DATA input
Transmitter-Receiver I/O pin
33
XFMR secondary
Secondary isolated winding, same phase as outer conducter
34
XFMR primary/
TX DATA output
Transformer lead for connection to outer conductor of tri-axial



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