MMDFS2P102

5

Motorola TMOS Product Preview Data

TYPICAL FET ELECTRICAL CHARACTERISTICS

Mounted on 2

″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″

thick single sided) with one die operating, 10 s max.

Figure 7. Capacitance Variation

Figure 8. Gate–To–Source and

Drain–To–Source Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation

versus Gate Resistance

Figure 10. Diode Forward Voltage versus

Current

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

5.0

20

–10

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

1200

800

1000

600

QG, TOTAL GATE CHARGE (nC)

16

0

6.0

4.0

2.0

0

100

1.0

RG, GATE RESISTANCE (OHMS)

1000

100

10

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

0.5

2.0

1.6

1.2

0.8

0.4

0

0.7

0.1

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

0.1

0.01

TJ, STARTING JUNCTION TEMPERATURE (°C)

50

150

25

350

300

50

0

1.0

400

200

0

– 5.0

0

10

4.0

8.0

12

12

10

0.9

1.1

1.3

1.5

10

1.0

75

100

125

100

15

100

10

100

10

8.0

150

200

250

ID = 6.0 A

VDS = 0 VGS = 0

TJ = 25°C

VGS = 0 V

TJ = 25°C

Ciss

Ciss

Coss

Crss

Crss

ID = 2.0 A

TJ = 25°C

VDS

VGS

QT

Q2

Q1

Q3

td(off)

td(on)

tr

tf

RDS(on) LIMIT

THERMAL LIMIT

PACKAGE LIMIT

dc

10 ms

1.0 ms

100

ms

10

ms

VGS = 20 V

SINGLE PULSE

TC = 25°C

VGS

VDS

0

18

16

14

12

10

8.0

6.0

4.0

2.0