Data Sheet

AD5535B

Rev. A | Page 13 of 16

AD5535B-to-MC68HC11 Interface

The serial peripheral interface (SPI) on the MC68HC11 is

configured for master mode (MSTR = 1), clock polarity bit (CPOL)

= 0, and clock phase bit (CPHA) = 1. The SPI is configured by

writing to the SPI control register (SPCR). SCK of the MC68HC11

drives the SCLK of the AD5535B and the MOSI output drives

derived from a port line (PC7). When data is being transmitted

to the AD5535B, the SYNC pin is taken low (PC7).

Data appearing on the MOSI output is valid on the falling edge

of SCK. The MC68HC11 transfers only eight bits of data during

each serial transfer operation; therefore, three consecutive write

operations are necessary to transmit 19 bits of data. Data is

transmitted MSB first. It is important to left justify the data in

the SPDR register so that the first 19 bits transmitted contain

valid data. PC7 must be pulled low to start a transfer. PC7 is then

taken high and pulled low again before any further write cycles

can take place. Figure 17 shows the connection diagram.

Figure 17. AD5535B-to-MC68HC11 Interface

AD5535B-to-PIC16C6x/7x Interface

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit = 0. This is done by

writing to the synchronous serial port control register (SSPCON).

In this example, I/O port RA1 is being used to pulse SYNC and

to enable the serial port of the AD5535B. This microcontroller

transfers only eight bits of data during each serial transfer

operation; therefore, three consecutive write operations are

necessary to transmit 19 bits of data. Data is transmitted MSB

first. It is important to left justify the data in the SPDR register

so that the first 19 bits transmitted contain valid data. RA1 must

be pulled low to start a transfer. RA1 must then be brought high

and pulled low again before any further write cycles can take

place. Figure 18 shows the connection diagram.

Figure 18. AD5535B-to-PIC16C6x/7x Interface

AD5535B-to-8051 Interface

The AD5535B requires a clock synchronized to the serial data.

Therefore, the 8051 serial interface must operate in Mode 0. In

this mode, serial data exits the 8051 through RxD, and a shift

clock is output on TxD. The SYNC signal is derived from a port

line (P1.1). Figure 19 shows how the 8051 is connected to the

AD5535B. Because the AD5535B shifts data out upon the rising

edge of the shift clock and latches data in upon the falling edge,

the shift clock must be inverted. Note that the AD5535B also

requires its data to be MSB first. Because the 8051 outputs LSB

first, the transmit routine must take this into account.

Figure 19. AD5535B-to-8051 Interface

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5535B*

MC68HC11*

SCLK

SYNC

SCK

MOSI

PC7

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5535B*

PIC16C6x/7x*

SCLK

SYNC

SCK/RC3

SDI/RC4

RA1

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5535B*

8051*

SCLK

SYNC

TxD

RxD

P1.1