ADP5586ACBZ-03-R7 datasheet(4/44 Pages) AD

4 / 44 page

ADP5586

Data Sheet

Rev. 0 | Page 4 of 44

I2C TIMING SPECIFICATIONS

Table 2.

Parameter

Description

Min

Max

Unit

I2C TIMING SPECIFICATIONS

Delay from UVLO/RST Inactive to I2C Access

μs

fSCL

SCL clock frequency

1000

kHz

tHIGH

SCL high time

0.26

μs

tLOW

SCL low time

0.5

μs

tSU; DAT

Data setup time

tHD; DAT

Data hold time

μs

tSU; STA

Setup time for repeated start

0.26

μs

tHD; STA

Hold time for start/repeated start

0.26

μs

tBUF

Bus free time for stop and start conditions

0.5

μs

tSU; STO

Setup time for stop condition

0.26

μs

tVD; DAT

Data valid time

0.45

μs

tVD; ACK

Data valid acknowledge

0.45

μs

Rise time for SCL and SDA

120

Fall time for SCL and SDA

120

tSP

Pulse width of suppressed spike

CB1

Capacitive load for each bus line

550

1 CB is the total capacitance of one bus line in picofarads (pF).

Timing Diagram

SDA

SCL

SDA

SCL

FIRST CLOCK CYCLE

NINTH CLOCK

fSCL

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

tHIGH

tVD; DAT

tSU; DAT

tSU; STA

tHD; DAT

tHD; STA

tVD; ACK

tSP

tSU; STO

tBUF

tLOW

tHD; STA

VIL = 0.3V × VDD

VIH = 0.7V × VDD

Figure 2. I2C Interface Timing Diagram

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