ADT7420UCPZ-R2 datasheet(5/24 Pages) AD

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Data Sheet

ADT7420

Rev. 0 | Page 5 of 24

I2C TIMING SPECIFICATIONS

TA = −40°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns

(10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SERIAL INTERFACE1

See Figure 2

SCL Frequency

400

kHz

SCL High Pulse Width, tHIGH

0.6

μs

SCL Low Pulse Width, tLOW

1.3

μs

SCL, SDA Rise Time, tR

0.3

μs

SCL, SDA Fall Time, tF

0.3

μs

Hold Time (Start Condition), tHD:STA

0.6

μs

After this period, the first clock is generated

Setup Time (Start Condition), tSU:STA

0.6

μs

Relevant for repeated start condition

Data Setup Time, tSU:DAT

0.02

μs

Setup Time (Stop Condition), tSU:STO

0.6

μs

Data Hold Time, tHD:DAT (Master)

0.03

μs

Bus-Free Time (Between Stop and Start Condition), tBUF

1.3

μs

Capacitive Load for Each Bus Line, CB

400

1 Sample tested during initial release to ensure compliance.

Timing Diagram

tLOW

tHD:STA

tHD:DAT

tSU:DAT

tSU:STA

tHD:STA

tSU:STO

tHIGH

SCL

SDA

tBUF

Figure 2. Serial Interface Timing Diagram

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