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2

Unit Loading/Fan Out

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Z

= High Impedance

Functional Description

The 74F257A is a quad 2-input multiplexer with 3-STATE

outputs. It selects four bits of data from two sources under

control of a Common Data Select input. When the Select

selected inputs appears at the outputs in true (non-

inverted) form. The device is the logic implementation of a

4-pole, 2-position switch where the position of the switch is

determined by the logic levels supplied to the Select input.

The logic equation for the outputs is shown below:

When the Output Enable input (OE) is HIGH, the outputs

are forced to a high impedance OFF state. If the outputs

are tied together, all but one device must be in the high

impedance state to avoid high currents that would exceed

the maximum ratings. Designers should ensure the Output

Enable signals to 3-STATE devices whose outputs are tied

together are designed so there is no overlap.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

S

Common Data Select Input

1.0/1.0

20

µA/−0.6 mA

OE

3-STATE Output Enable Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

Data Inputs from Source 0

1.0/1.0

20

µA/−0.6 mA

Data Inputs from Source 1

1.0/1.0

20

µA/−0.6 mA

3-STATE Multiplexer Outputs

150/40 (33.3)

−3 mA/24 mA (20 mA)

Output

Select

Data

Output

Enable

Input

Inputs

OE

S

Z

HX

X

X

Z

LH

X

L

L

LH

X

H

H

LL

L

X

L

LL

H

X

H