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WM8903 데이터시트(PDF) 21 Page - Wolfson Microelectronics plc |
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WM8903 데이터시트(HTML) 21 Page - Wolfson Microelectronics plc |
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21 / 178 page ![]() Production Data WM8903 w PD, Rev 4.5, June 2012 21 SLAVE MODE Figure 3 Audio Interface Timing – Slave Mode Audio Interface Timing – Slave Mode PARAMETER SYMBOL MIN TYP MAX UNIT BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRC set-up time to BCLK rising edge tLRSU 10 ns LRC hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 30 ns DACDAT set-up time to BCLK rising edge tDS 20 ns Note: BCLK period must always be greater than or equal to MCLK period. |
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