VDrive2 Vinculum VNC1L Module

Datasheet Version 0.99

© Future Technology Devices International Ltd. 2007

Page 

2.3 SPI Interface Signal Descriptions and Timing Diagrams

Ta�le 3 - Data and Control ��us �ignal Mode �ptions - ��I Inter�ace

Pin No.

Name

Type

Description

�

�CLK

Input

��I Cloc� input�� 12MHz ma�imum.

4

�DI

Input

��I �erial Data Input

2

�D�

�utput

��I �erial Data �utput

6

C�

Input

��I Chip �elect Input

Figure 2 - ��I �lave Data �ead Cycle

SPICLK

SPI Data In

SPI Data Out

SPI CS

R/W ADD

D0

D1

D2

D3

D4

D5

D6

D7

1

1

0

From �tart - ��I C� must �e held high �or the entire read cycle�� and must �e ta�en low �or at least one cloc� period

aft�r th� r�ad i� co��p��t�d. Th� fir�t bit on S��I Data In i� th� R/W bit - inp�tting a ‘1’ h�r� a��o�� data to b� r�ad fro��

the chip. The ne�t �it is the address �it�� �DD�� which is used to indicate whether the data register (�0�) or the status

register (�1�) is read �rom. During the ��I read cycle a �yte o� data will start �eing output on ��I Data �ut on the ne�t

c�ock cyc�� aft�r th� addr��� bit�� MSB fir�t. �ft�r th� data ha� b��n c�ock�d o�t of th� chip�� th� �tat�� of S��I Data

�ut should �e chec�ed to see i� the data read is new data. � �0� level here on ��I Data �ut means that the data read

is new data. � �1� indicates that the data read is old data�� and the read cycle should �e repeated to get new data.

�emem�er that C� must �e held low �or at least one cloc� period �e�ore �eing ta�en high again to continue with the

ne�t read or write cycle.

Figure 3 - ��I �lave Data Write Cycle

SPICLK

SPI Data In

SPI Data Out

SPI CS

R/W ADD

D0

D1

D2

D3

D4

D5

D6

D7

1

0

0

From �tart - ��I C� must �e held high �or the entire write cycle�� and must �e ta�en low �or at least one cloc� period

aft�r th� �rit� i� co��p��t�d. Th� fir�t bit on S��I Data In i� th� R/W bit - inp�tting a ‘0’ h�r� a��o�� data to b� �ritt�n

to the chip. The ne�t �it is the address �it�� �DD�� which is used to indicate whether the data register (�0�) or the status

register (�1�) is written to. During the ��I write cycle a �yte o� data can �e input to ��I Data In on the ne�t cloc� cycle

aft�r th� addr��� bit�� MSB fir�t. �ft�r th� data ha� b��n c�ock�d in to th� chip�� th� �tat�� of S��I Data O�t �ho��d b�