MPC990 MPC991

TIMING SOLUTIONS

BR1333 — Rev 6

3

MOTOROLA

FUNCTION TABLE 2

fselFB2

fselFB1

fselFB0

QFB

0

0

0

0

0

0

1

1

0

1

0

1

÷2

÷4

÷6

÷8

1

1

1

1

0

0

1

1

0

1

0

1

÷8

÷16

÷24

÷32

FUNCTION TABLE 3

Control Pin

Logic ‘0’

Logic ‘1’

PLL_En

Enable PLL

Bypass PLL

VCO_Sel

fVCO

fVCO/2

Ref_Sel

xtal or ECL/PECL

Test_Clk

MR

—

Reset Outputs

SYNC_Sel

SYNC Outputs

Match Qc Outputs

Figure 2. MPC990/991 Logic Diagram

VCO

PHASE

DETECTOR

LPF

PLL_En

VCO_Sel

ECL_Clk

ECL_Clk

Test_Clk

Ref_Sel

Ext_FB

Ext_FB

Qa0

Qa0

Qa1

Qa1

Qa2

Qa2

Qa3

Qa3

Qb0

Qb0

Qb1

Qb1

Qb2

Qb2

Qb3

Qb3

Qc0

Qc0

Qc1

Qc1

Qc2

Qc2

Qd0

Qd0

Qd1

Qd1

QFB

QFB

FREQUENCY

GENERATOR

SYNC

MR

fsela0:3

fselFB0:2

SYNC_Sel

(Pulldown)

(Pulldown)

(Pulldown)

(Pulldown)

(Pulldown)

(Pulldown)

(Pulldown)

(Pulldown)

MPC991

MPC990

Xtal

Osc

NOTE: ECL_Clk, Ext_FB have internal pulldowns, while ECL_Clk, Ext_FB have external

pullups to ensure stability under open input conditions.