ADP124/ADP125

Data Sheet

Rev. C | Page 12 of 20

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP124/ADP125 are designed for operation with small,

space-saving ceramic capacitors, but these devices can function

with most commonly used capacitors as long as care is taken to

ensure an appropriate effective series resistance (ESR) value. The

ESR of the output capacitor affects the stability of the LDO control

loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or

less is recommended to ensure stability of the ADP124/ADP125.

The transient response to changes in load current is also affected by

the output capacitance. Using a larger value of output capacitance

improves the transient response of the ADP124/ADP125 to

dynamic changes in load current. Figure 30 and Figure 31 show

the transient responses for output capacitance values of 1 µF and

4.7 µF, respectively.

M400ns

A CH1

200mA

1

2

T

13.20%

1mA TO 500mA LOAD STEP

CH1

W

CH2 50.0mV

B

W

M400ns

A CH1

200mA

1

2

T

13.60%

1mA TO 500mA LOAD STEP

CH1

W

CH2 50.0mV

B

W

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces the circuit

sensitivity to the printed circuit board (PCB) layout, especially

when a long input trace or high source impedance is encountered.

If greater than 1 µF of output capacitance is required, the input

capacitor should be increased to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADP124/ADP125, as long as the capacitor meets the minimum

capacitance and maximum ESR requirements. Ceramic capacitors

are manufactured with a variety of dielectrics, each with different

behavior over temperature and applied voltage. Capacitors must

have an adequate dielectric to ensure the minimum capacitance

over the necessary temperature range and dc bias conditions.

Using an X5R or X7R dielectric with a voltage rating of 6.3 V or

10 V is recommended. However, using Y5V and Z5U dielectrics

are not recommended for any LDO, due to their poor temperature

and dc bias characteristics.

Figure 32 depicts the capacitance vs. capacitor voltage bias charac-

teristics of an 0402, 1 µF, 10 V X5R capacitor. The voltage stability

of a capacitor is strongly influenced by the capacitor size and the

voltage rating. In general, a capacitor in a larger package or of a

higher voltage rating exhibits better stability. The temperature

variation of the X5R dielectric is about ±15% over the −40°C to

+85°C temperature range and is not a function of package or

voltage rating.

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

0

1

2

3

4

5

6

7

BIAS VOLTAGE (V)

Figure 32. Capacitance vs. Capacitor Voltage Bias Characteristics

Equation 1 can be used to determine the worst-case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage.

(1)

where:

C is the rated capacitance value.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.