JS28F128P33TF70A datasheet(19/88 Pages) MICROCHIP

19 / 88 page

Datasheet

Jul 2011

Order Number:208034-04

P33-65nm SBC

Protection

Lock Block

Write

0x60

Write

0x01

Unlock Block

Write

0x60

Write

0xD0

Lock-down Block

Write

0x60

Write

0x2F

Program OTP

Write

PRA

0xC0

Write

OTP-RA

OTP-D

Program Lock

Write

LRA

0xC0

Write

LRA

LRD

Configuration

Program Read

Configuration

Write

RCD

0x60

Write

RCD

0x03

Others

Blank Check

Write

0xBC

Write

Extended Function

Interface(5)

Write

0xEB

Write

Sub-Op

code

Notes:

First command cycle address should be the same as the operation’s target address.

DBA = Device Base Address

DnA = Address within the device.

IA = Identification code address offset.

CFI-A = Read CFI address offset.

WA = Word address of memory location to be written.

BA = Address within the block.

OTP-RA = OTP Register address.

LRA = Lock Register address.

RCD = Read Configuration Register data on A[16:1].

ID = Identifier data.

CFI-D = CFI data on DQ[15:0].

SRD = Status Register data.

WD = Word data.

N = Word count of data to be loaded into the write buffer.

OTP-D = OTP Register data.

LRD = Lock Register data.

The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This

is followed by up to 256 words of data.Then the confirm command (0xD0) is issued, triggering the array programming

operation.

The confirm command (0xD0) is followed by the buffer data.

The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1≤ N ≤ 256. The subsequent cycles load data

words into the program buffer at a specified address until word count is achieved, after the data words are loaded, the

final cycle is the confirm cycle 0xD0).

Table 6:

Command Bus Cycles (Sheet 2 of 2)

Mode

Command

Bus

Cycles

First Bus Cycle

Second Bus Cycle

Oper

Addr(1)

Data(2)

Oper

Addr(1)

Data(2)

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