LPC4350_13 datasheet(72/153 Pages) NXP

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LPC4350_30_20_10

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Product data sheet

Rev. 4 — 26 March 2013

72 of 153

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

After a few commands configure the interface at startup, the entire flash content is

accessible as normal memory using byte, halfword, and word accesses by the processor

and/or DMA channels. Simple sequences of commands handle erasing and

programming.

Many serial flash devices use a half-duplex command-driven SPI protocol for device setup

and initialization and then move to a half-duplex, command-driven 4-bit protocol for

normal operation. Different serial flash vendors and devices accept or require different

commands and command formats. SPIFI provides sufficient flexibility to be compatible

with common flash devices and includes extensions to help insure compatibility with future

devices.

7.17.2.1

Features

• Interfaces to serial flash memory in the main memory map.

• Supports classic and 4-bit bidirectional serial protocols.

• Half-duplex protocol compatible with various vendors and devices.

• Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to

52 MB per second.

• Supports DMA access.

7.17.3 SD/MMC card interface

The SD/MMC card interface supports the following modes to control:

• Secure Digital memory (SD version 3.0)

• Secure Digital I/O (SDIO version 2.0)

• Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)

• MultiMedia Cards (MMC version 4.4)

7.17.4 External Memory Controller (EMC)

The LPC4350/30/20/10 EMC is a Memory Controller peripheral offering support for

asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it

can be used as an interface with off-chip memory-mapped devices and peripherals.

7.17.4.1

Features

• Dynamic memory interface support including single data rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and NOR flash,

with or without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8/16/32 data and 24 address lines-wide static memory support.

• 16 bit and 32 bit wide chip select SDRAM memory support.

• Static memory features include:

– Asynchronous page mode read

– Programmable Wait States

– Bus turnaround delay

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