MCP9844 datasheet(10/44 Pages) MICROCHIP

10 / 44 page

MCP9844

DS20005192A-page 10

 2013 Microchip Technology Inc.

4.1.5

DATA VALID

After the Start condition, each bit of data in the

transmission needs to be settled for a time specified by

tSU-DATA before SCL toggles from low-to-high (see

Serial Interface Timing Specifications

table).

4.1.6

ACKNOWLEDGE (ACK/NAK)

Each receiving device, when addressed, is obliged to

generate an ACK bit after the reception of each byte.

The master device must generate an extra clock pulse

for ACK to be recognized.

The acknowledging device pulls down the SDA line for

tSU-DATA before the low-to-high transition of SCL from

the master. SDA also needs to remain pulled down for

tH-DATA after a high-to-low transition of SCL.

During read, the master must signal an End-of-Data

(EOD) to the slave by not generating an ACK bit (NAK)

once the last bit has been clocked out of the slave. In

this case, the slave will leave the data line released to

enable the master to generate the Stop condition.

4.1.7

TIME OUT (TOUT)

If the SCL stays low or high for time specified by tOUT,

the MCP9844 resets the serial interface. This dictates

the minimum clock speed as specified in the specifica-

tion.

MCP9844 데이터시트(PDF) 10 Page - Microchip Technology