MRF24WB0MB datasheet(11/38 Pages) MICROCHIP

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 2010-2013 Microchip Technology Inc.

DS70632C-page 11

MRF24WB0MA/MRF24WB0MB

2.0

CIRCUIT DESCRIPTION

The

MRF24WB0MA/MRF24WB0MB

interfaces

Microchip’s PIC18, PIC24, dsPIC33, and PIC32

microprocessors

with

minimal

external

components through digital-only connections. This

section details use of the module, starting with an

example host connection as shown in Figure 2-1.

2.1

Schematic

FIGURE 2-1:

MRF24WB0MA/MRF24WB0MB EXAMPLE APPLICATION SCHEMATIC

2.2

Power-On Sequence

The internal regulators for the digital and analog core

power

supplies

are

disabled

driving

the

HIBERNATE pin high. Figure 2-2 shows the power up

sequence for the MRF24WB0MA/MRF24WB0MB.

An internal Power-on Reset (POR) circuit which keeps

the

module

Reset

until

VDD

within

the

specification. The Hibernate and Reset signals are also

used to control startup. In Figure 2-2, section A is

controlled by the internal POR and section B is an

allowance for the SPI bus to stabilize when the module

supplies are enabled. After Hibernate is disabled, the

host software provides 1mS of startup to allow the SPI

to stabilize. This time is pre-programmed into the host

driver, and may need to be increased if insufficient

initial drive current is not provided to the MRF24WB0M

module. Section C is the driver controlled release from

Reset period. This takes approximately 300 mS and is

monitored by the stack driver. No additional time needs

to be provided by user software for startup.

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