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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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rfPIC12F675F 데이터시트(PDF) 21 Page - Microchip Technology |
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rfPIC12F675F 데이터시트(HTML) 21 Page - Microchip Technology |
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21 / 136 page  2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 21 rfPIC12F675 3.3.3 GP2/AN2/T0CKI/INT/COUT Figure 3-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D • the clock input for TMR0 • an external edge triggered interrupt • a digital output from the comparator FIGURE 3-2: BLOCK DIAGRAM OF GP2 3.3.4 GP3/MCLR/VPP Figure 3-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset FIGURE 3-3: BLOCK DIAGRAM OF GP3 I/O pin VDD VSS D Q CK Q D Q CK Q D Q CK Q D Q CK Q VDD D EN Q D EN Q Weak Analog Input Mode Data Bus WR WPU RD WPU RD PORT WR PORT WR TRISIO RD TRISIO WR IOC RD IOC Interrupt-on-Change To A/D Converter 0 1 COUT COUT Enable To INT To TMR0 Analog Input Mode GPPU RD PORT Analog Input Mode I/O pin VSS D Q CK Q D EN Q Data Bus RD PORT RD PORT WR IOC RD IOC Interrupt-on-Change RESET MCLRE RD TRISIO VSS D EN Q MCLRE |
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