PIC24FV16KA301-ISLASHSS datasheet(63/364 Pages) MICROCHIP

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DS39995D-page 63

PIC24FV32KA304 FAMILY

6.0

DATA EEPROM MEMORY

The data EEPROM memory is a Nonvolatile Memory

(NVM), separate from the program and volatile data

RAM. Data EEPROM memory is based on the same

Flash technology as program memory, and is optimized

for both long retention and a higher number of

erase/write cycles.

The data EEPROM is mapped to the top of the user

program memory space, with the top address at pro-

gram memory address, 7FFE00h to 7FFFFFh. The

size of the data EEPROM is 256 words in the

PIC24FV32KA304 family devices.

The data EEPROM is organized as 16-bit wide

memory. Each word is directly addressable, and is

readable and writable during normal operation over the

entire VDD range.

Unlike the Flash program memory, normal program

execution is not stopped during a data EEPROM

program or erase operation.

The data EEPROM programming operations are

controlled using the three NVM Control registers:

• NVMCON: Nonvolatile Memory Control Register

• NVMKEY: Nonvolatile Memory Key Register

• NVMADR: Nonvolatile Memory Address Register

6.1

NVMCON Register

The NVMCON register (Register 6-1) is also the primary

control register for data EEPROM program/erase

operations. The upper byte contains the control bits

used to start the program or erase cycle, and the flag bit

to indicate if the operation was successfully performed.

The lower byte of NVMCOM configures the type of NVM

operation that will be performed.

6.2

NVMKEY Register

The NVMKEY is a write-only register that is used to

prevent accidental writes or erasures of data EEPROM

locations.

To start any programming or erase sequence, the

following instructions must be executed first, in the

exact order provided:

Write 55h to NVMKEY.

Write AAh to NVMKEY.

After this sequence, a write will be allowed to the

NVMCON register for one instruction cycle. In most

cases, the user will simply need to set the WR bit in the

NVMCON register to start the program or erase cycle.

Interrupts should be disabled during the unlock

sequence.

The MPLAB® C30 C compiler provides a defined library

procedure (builtin_write_NVM) to perform the

unlock sequence. Example 6-1 illustrates how the

unlock sequence can be performed with in-line

assembly.

EXAMPLE 6-1:

DATA EEPROM UNLOCK SEQUENCE

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on

Data EEPROM, refer to the “PIC24F

Family Reference Manual”, Section 5.

“Data EEPROM” (DS39720).

//Disable Interrupts For 5 instructions

asm volatile

("disi #5");

//Issue Unlock Sequence

asm volatile

("mov #0x55, W0

\n"

"mov W0, NVMKEY

\n"

"mov #0xAA, W1

\n"

"mov W1, NVMKEY

\n");

// Perform Write/Erase operations

asm volatile

("bset NVMCON, #WR \n"

"nop

\n"

"nop

\n");

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