AD8115AST datasheet(6/32 Pages) AD

6 / 32 page

AD8114/AD8115

Rev. B | Page 6 of 32

TIMING CHARACTERISTICS (PARALLEL)

Table 4. Timing Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Data Setup Time

CLK Pulse Width

100

Data Hold Time

CLK Pulse Separation

100

CLK to UPDATE Delay

UPDATE Pulse Width

Propagation Delay, UPDATE to Switch On or Off

–

CLK, UPDATE Rise and Fall Times

–

100

RESET Time

–

200

Table 5. Logic Levels

VIH

VIL

VOH

VOL

IIH

IIL

IOH

IOL

RESET, SER/PAR,

CLK, D0, D1, D2,

D3, D4, A0, A1, A2,

A3, CE, UPDATE

RESET, SER/PAR,

CLK, D0, D1, D2,

D3, D4, A0, A1, A2,

A3, CE, UPDATE

DATA OUT

RESET, SER/PAR,

CLK, D0, D1, D2,

D3, D4, A0, A1, A2,

A3, CE, UPDATE

RESET, SER/PAR,

CLK, D0, D1, D2,

D3, D4, A0, A1, A2,

A3, CE, UPDATE

DATA

OUT

DATA

OUT

2.0 V min

0.8 V max

2.7 V min

0.5 V max

20 µA max

−400 µA min

−400 µA

max

3.0 mA

min

D0–D3

A0–A2

CLK

1 = LATCHED

UPDATE

0 = TRANSPARENT

Figure 3. Timing Diagram, Parallel Mode

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