ADAU1461WBCPZ-R7 datasheet(37/88 Pages) AD

37 / 88 page

ADAU1461

Rev. 0 | Page 37 of 88

The R/W bit determines the direction of the data. A Logic 0 on

the LSB of the first byte means that the master will write infor-

mation to the peripheral, whereas a Logic 1 means that the

master will read information from the peripheral after writing

the subaddress and repeating the start address. A data transfer

takes place until a stop condition is encountered. A stop

condition occurs when SDA transitions from low to high while

SCL is held high.

shows the timing of an I2C write,

and

shows an I2C read.

Figure 49

Figure 50

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, the ADAU1461 immediately

jumps to the idle condition. During a given SCL high period,

the user should only issue one start condition, one stop condition,

or a single stop condition followed by a single start condition. If

an invalid subaddress is issued by the user, the ADAU1461 does

not issue an acknowledge and returns to the idle condition.

If the user exceeds the highest subaddress while in autoincrement

mode, one of two actions is taken. In read mode, the ADAU1461

outputs the highest subaddress register contents until the master

device issues a no acknowledge, indicating the end of a read. A

no acknowledge condition is where the SDA line is not pulled

low on the ninth clock pulse on SCL. If the highest subaddress

location is reached while in write mode, the data for the invalid

byte is not loaded into any subaddress register, a no acknowledge

is issued by the ADAU1461, and the part returns to the idle

condition.

R/W

SCL

SDA

(CONTINUED)

SCL

(CONTINUED)

ADDR0

ADDR1

START BY

MASTER

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

SUBADDRESS BYTE 1

FRAME 3

FRAME 4

ACK BY

ADAU1461

ACK BY

ADAU1461

ACK BY

ADAU1461

ACK BY

ADAU1461

STOP BY

MASTER

SUBADDRESS BYTE 2

DATA BYTE 1

Figure 49. I2C Write to ADAU1461 Clocking

R/W

SCL

SDA

(CONTINUED)

SCL

(CONTINUED)

START BY

MASTER

FRAME 2

SUBADDRESS BYTE 1

FRAME 1

CHIP ADDRESS BYTE

ACK BY

ADAU1461

ACK BY

ADAU1461

ACK BY

ADAU1461

ACK BY

ADAU1461

REPEATED

START BY MASTER

SDA

(CONTINUED)

SCL

(CONTINUED)

FRAME 3

SUBADDRESS BYTE 2

FRAME 4

CHIP ADDRESS BYTE

FRAME 5

READ DATA BYTE 1

STOP BY

MASTER

ACK BY

MASTER

R/W

ADDR0

ADDR1

Figure 50. I2C Read from ADAU1461 Clocking

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