PIC16F883 datasheet(91/338 Pages) MICROCHIP

91 / 338 page

 2006-2012 Microchip Technology Inc.

DS41291G-page 91

PIC16F882/883/884/886/887

8.2

Comparator Control

Each comparator has a separate control and

Configuration register: CM1CON0 for Comparator C1

and CM2CON0 for Comparator C2. In addition,

Comparator C2 has a second control register,

CM2CON1, for controlling the interaction with Timer1 and

simultaneous reading of both comparator outputs.

The CM1CON0 and CM2CON0 registers (see Registers

8-1 and 8-2, respectively) contain the control and Status

bits for the following:

• Enable

• Input selection

• Reference selection

•Output selection

• Output polarity

8.2.1

COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

8.2.2

COMPARATOR INPUT SELECTION

The CxCH<1:0> bits of the CMxCON0 register direct

one of four analog input pins to the comparator

inverting input.

8.2.3

COMPARATOR REFERENCE

SELECTION

Setting the CxR bit of the CMxCON0 register directs an

internal voltage reference or an analog input pin to the

non-inverting

input

the

comparator.

See

Section 8.10 “Comparator Voltage Reference” for

more information on the internal voltage reference

module.

8.2.4

COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CM2CON1 register. In order

to make the output available for an external connection,

the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

8.2.5

COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

Table 8-1 shows the output state versus input

conditions, including polarity control.

8.3

Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the

comparator differs from the settling time of the voltage

reference. Therefore, both of these times must be

considered when determining the total response time

to a comparator input change. See the Comparator and

Voltage Reference specifications in Section 17.0

“Electrical Specifications” for more details.

Note:

To use CxIN+ and CxIN- pins as analog

inputs, the appropriate bits must be set in

the ANSEL and ANSELH registers and

the corresponding TRIS bits must also be

set to disable the output drivers.

Note 1: The CxOE bit overrides the PORT data

latch. Setting the CxON has no impact on

the port override.

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

TABLE 8-1:

COMPARATOR OUTPUT

STATE VS. INPUT

CONDITIONS

Input Condition

CxPOL

CxOUT

CxVIN- > CxVIN+

CxVIN- < CxVIN+

CxVIN- > CxVIN+

CxVIN- < CxVIN+

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