©2012 Silicon Storage Technology, Inc.

DS25024C

10/12

22

8 Mbit 1.8V SPI Serial Flash

SST25WF080

Not Recommended for New Designs

Write-Status-Register (WRSR)

The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of

the status register. CE# must be driven low before the command sequence of the WRSR instruction is

entered and driven high before the WRSR instruction is executed. See Figure 21 for EWSR or WREN

and WRSR instruction sequences.

Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to

‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status register, but

cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and

the BPL, BP0, BP1, BP2, and BP3 bits in the status register can all be changed. As long as BPL bit is

the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this

case, a single WRSR instruction can set the BPL bit to ‘1’ to lock down the status register as well as

altering the BP0, BP1, BP2, and BP3 bits at the same time. See Table 3 for a summary description of

WP# and BPL functions.

Figure 21:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Sta-

tus-Register (WRSR) Sequence

Enable-Hold (EHLD)

The 8-bit command, AAH, Enable-Hold instruction enables the HOLD functionality of the RST#/

HOLD# pin. CE# must remain active low for the duration of the Enable-Hold instruction sequence. CE#

must be driven high before the instruction is executed. See Figure 22 for the Enable-Hold instruction

sequence.

Figure 22:Enable-Hold Sequence

1203 F20.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

REGISTER IN

7 65 4321 0

MSB

MSB

MSB

01

MODE 3

SCK

SI

SO

CE#

MODE 0

50 or 06

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CE#

SO

SI

SCK

01 2 3 4 5 6 7

AA

HIGH IMPEDANCE

MODE 0

MODE 3

1203 F21.0

MSB