ADAU1761BCPZ-R7 datasheet(61/92 Pages) AD

61 / 92 page

ADAU1761

Rev. C | Page 61 of 92

R12: ALC Control 1, 16,402 (0x4012)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ALCHOLD[3:0]

ALCTARG[3:0]

Table 46. ALC Control 1 Register

Bits

Bit Name

Description

[7:4]

ALCHOLD[3:0]

ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before

increasing the gain to achieve the target level. The recommended minimum setting is 21 ms (0011) to prevent

distortion of low frequency signals. The hold time doubles with every 1-bit increase.

Setting

Hold Time

0000

2.67 ms (default)

0001

5.34 ms

0010

10.68 ms

0011

21.36 ms

0100

42.72 ms

0101

85.44 ms

0110

170.88 ms

0111

341.76 ms

1000

683.52 ms

1001

1.367 sec

1010

2.7341 sec

1011

5.4682 sec

1100

10.936 sec

1101

21.873 sec

1110

43.745 sec

1111

87.491 sec

[3:0]

ALCTARG[3:0]

ALC target. The ALC target sets the desired ADC input level. The PGA gain is adjusted by the ALC to reach this

target level. The recommended target level is between −16 dB and −10 dB to accommodate transients without

clipping the ADC.

Setting

ALC Target

0000

−28.5 dB (default)

0001

−27 dB

0010

−25.5 dB

0011

−24 dB

0100

−22.5 dB

0101

−21 dB

0110

−19.5 dB

0111

−18 dB

1000

−16.5 dB

1001

−15 dB

1010

−13.5 dB

1011

−12 dB

1100

−10.5 dB

1101

−9 dB

1110

−7.5 dB

1111

−6 dB

ADAU1761BCPZ-R7 데이터시트(PDF) 61 Page - Analog Devices

ADAU1761BCPZ-R7 데이터시트(HTML) 61 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

데이터시트 다운로드

링크 URL