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AD9789BBCZ 데이터시트(PDF) 30 Page - Analog Devices

부품명 AD9789BBCZ
상세설명  14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
PDF  76 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9789BBCZ 데이터시트(HTML) 30 Page - Analog Devices

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AD9789
Rev. A | Page 30 of 76
Table 16. Interrupt Status/Clear Register (Address 0x04)
Bit
Name
Description
7
PARERR
If this bit is set to 1, one or more parity errors has occurred. Writing a 1 to this bit clears the interrupt.
6
BISTDONE
If this bit is set to 1, the BIST has reached the terminal state. Writing a 1 to this bit clears the interrupt.
5
PARMSET
If this bit is set to 1, the parameter update register (Address 0x24) has been updated. Writing a 1 to this bit clears
the interrupt.
4
PARMCLR
If this bit is set to 1, the parameter update register (Address 0x24) has been cleared. Writing a 1 to this bit clears
the interrupt.
3
LOCKACQ
If this bit is set to 1, proper data handoff between the digital engine and the DAC core is occurring.
2
LOCKLOST
If this bit is set to 1, proper data handoff between the digital engine and the DAC core has been lost. Writing a 1
to this bit clears the interrupt.
1
SATERR
If this bit is set to 1, one or more saturation errors (overflow into 16× interpolator) has occurred. Writing a 1 to
this bit clears the interrupt.
0
Reserved
Reserved.
Table 17. Channel Enable Register (Address 0x05)
Bit
Bit Name
Description
[7:4]
Reserved
Reserved.
[3:0]
CHANEN[3:0]
A Logic 1 in any bit position enables the corresponding channel; 0000 means that all channels are disabled.
Setting
Channels Enabled
0000
All channels disabled.
0001
Channel 0 enabled.
0010
Channel 1 enabled.
0011
Channel 0 and Channel 1 enabled.
…
…
1110
Channel 1, Channel 2, and Channel 3 enabled.
1111
All channels enabled.
Table 18. Bypass Register (Address 0x06)
Bit
Bit Name
Description
7
QAM
If this bit is set to 1, the QAM mappers are bypassed.
6
SRRC
If this bit is set to 1, the square root raised cosine (SRRC) filters are bypassed.
5
Reserved
Reserved.
[4:0]
INT[4:0]
A Logic 1 in any bit position bypasses the corresponding interpolation filter. The preferred order for bypassing
interpolation filters is to first bypass Filter 0, then Filter 1, and so on.
Setting
Interpolation Filters Bypassed
00000
All interpolation filters enabled.
00001
Interpolation Filter 0 bypassed.
00010
Interpolation Filter 1 bypassed.
00011
Interpolation Filter 0 and Interpolation Filter 1 bypassed.
…
…
01111
Interpolation Filter 0, Interpolation Filter 1, Interpolation Filter 2, and Interpolation Filter 3
bypassed.
…
…
11111
All interpolation filters bypassed.



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