전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

STM32F101ZGT6 데이터시트(PDF) 90 Page - STMicroelectronics

부품명 STM32F101ZGT6
상세설명  XL-density access line, ARM-based 32-bit MCU with 768 KB to 1 MB Flash, 15 timers, 1 ADC and 10 communication interfaces
PDF  108 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101ZGT6 데이터시트(HTML) 90 Page - STMicroelectronics

Back Button STM32F101ZGT6 Datasheet HTML 86Page - STMicroelectronics STM32F101ZGT6 Datasheet HTML 87Page - STMicroelectronics STM32F101ZGT6 Datasheet HTML 88Page - STMicroelectronics STM32F101ZGT6 Datasheet HTML 89Page - STMicroelectronics STM32F101ZGT6 Datasheet HTML 90Page - STMicroelectronics STM32F101ZGT6 Datasheet HTML 91Page - STMicroelectronics STM32F101ZGT6 Datasheet HTML 92Page - STMicroelectronics STM32F101ZGT6 Datasheet HTML 93Page - STMicroelectronics STM32F101ZGT6 Datasheet HTML 94Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 90 / 108 page
background image
Electrical characteristics
STM32F101xF, STM32F101xG
90/108
Doc ID 17143 Rev 2
Table 54.
SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
18
MHz
Slave mode
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
DuCy(SCK)
SPI slave input clock duty
cycle
Slave mode
30
70
%
tsu(NSS)
(2)
NSS setup time
Slave mode
4tPCLK
ns
th(NSS)
(2)
NSS hold time
Slave mode
2tPCLK
tw(SCKH)
(2)
tw(SCKL)
(2)
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
tsu(MI)
(2)
tsu(SI)
(2)
Data input setup time
Master mode
5
Slave mode
5
th(MI)
(2)
Data input hold time
Master mode
5
th(SI)
(2)
Slave mode
4
ta(SO)
(2)(3)
Data output access time
Slave mode, fPCLK = 20 MHz
0
3tPCLK
tdis(SO)
(2)(4)
Data output disable time
Slave mode
2
10
tv(SO)
(2)(1)
Data output valid time
Slave mode (after enable edge)
25
tv(MO)
(2)(1)
Data output valid time
Master mode (after enable edge)
5
th(SO)
(2)
Data output hold time
Slave mode (after enable edge)
15
th(MO)
(2)
Master mode (after enable edge)
2
1.
Remapped SPI1 characteristics to be determined.
2.
Based on characterization, not tested in production.
3.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com