MPC8260EC datasheet(2/41 Pages) FREESCALE

2 / 41 page

MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Features

Figure 1 shows the block diagram for the MPC8260.

Figure 1. MPC8260 Block Diagram

Features

The major features of the MPC8260 are as follows:

•

Dual-issue integer core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 133–200 MHz (150–200 MHz for the

MPC8255)

— Separate 16-Kbyte data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— PowerPC architecture-compliant memory management unit (MMU)

16 Kbytes

G2 Core

I-Cache

I-MMU

16 Kbytes

D-Cache

D-MMU

Communication Processor Module (CPM)

Timers

Parallel I/O

Baud Rate

Generators

24 Kbytes

32-bit RISC Microcontroller

and Program ROM

Serial

DMAs

2 Virtual

IDMAs

Bridge

Memory Controller

Clock Counter

System Functions

System Interface Unit

(SIU)

Local Bus

32 bits, up to 66 MHz

MCC11

MCC2

FCC1

FCC2

FCC31

SCC1

SCC2

SCC3

SCC4

SMC1

SMC2

SPI

I2C

Serial Interface

3 MII

2 UTOPIA

Ports

60x Bus

Dual-Port RAM

Interrupt

Controller

Time Slot Assigner

8 TDM Ports2

Non-Multiplexed

I/O

60x-to-Local

Bus Interface Unit

Notes:

1 Not on MPC8255

2 4 on the MPC8255

3 2 on the MPC8255

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